• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The present invention can optimize the size of the output driver, that is, the size of the PMOS by using the difference in driving capability between the pull-up PMOS and the pull-down NMOS constituting the output driver and the metal line loading from the sense amplifier stage to the output driver. To provide a synchronous memory device, to which the present invention connects the first latch means and the second latch means to the first metal line and the second metal line, respectively, the positive output and the sub output lines of the sense amplifier stage. The first latch means is subjected to the loading influence of the first metal line from the positive output end of the sense amplifier stage to the input end of the first latch, and the PMOS of the output driver provided from the output end of the first latch to the PMOS of the provided output driver The second latch means is connected to the second output device from the sub output end of the sense amplifier stage so that the second latch means is hardly affected by the loading. The connection is configured such that the input end of the dimension end is hardly influenced by the loading of the second metal line, and the output terminal of the second latch means is connected to the NMOS of the output driver provided with little effect on the loading of the second metal line. It is done.
    公开号:KR19980052437A
    申请号:KR1019960071425
    申请日:1996-12-24
    公开日:1998-09-25
    发明作者:김택무
    申请人:김영환；현대전자산업 주식회사；
    IPC主号:
    专利说明:

    Synchronous memory device for size optimization of output drivers
    The present invention relates to a synchronous memory device, and more particularly, to a synchronous memory device having an improved structure on an output path for reading data in order to optimize the size of an output driver.
    As is well known, the output stage of a synchronous memory device has a sense amplifier stage 10 for sensing and amplifying data from a memory cell and outputting a positive signal and a negative signal, respectively, as shown in FIG. 1, and a cycle through the sense amplifier. It consists of one latch stage 20 for storing the data read during the cycle, and an output driver 30 for outputting the data to the outside. The output driver stage 30 is composed of a pull-up PMOS transistor (PMOS) and a pull-down NMOS transistor (NMOS), which are pulled up and pulled down, and the two transistors are sized to drive a large load in the rear stage. Significantly larger than other transistors.
    When the normal process is used in this structure, the ratio of the size of the PMOS transistor and the NMOS transistor constituting the output driver is drawn about 1.5 to 2 times as large as the PMOS transistor. As device process technology continues to develop, the total area of memory devices will be determined by the size of the output driver. In particular, memory devices employing 2.5VI / O interfaces to reduce the trend toward device bit-wide and resulting output noise require that the size of the PMOS transistor be relatively larger than it is now. do.
    The present invention utilizes the difference in driving capability between the pull-up PMOS transistor and the pull-down NMOS transistor constituting the output driver, and the size of the output driver using the metal line loading from the sense amplifier stage to the output driver, that is, the PMOS transistor. It is an object of the present invention to provide a synchronous memory device capable of optimizing the size thereof.
    1 is an output structure of a conventional synchronous memory device;
    2 is an output structure of a synchronous memory device according to an embodiment of the present invention.
    * Description of the symbols for the main parts of the drawings *
    10: sense amplification stage
    20a, 20b: first and second latches
    30: output driver
    In order to achieve the above object, the present invention connects the first latch means and the second latch means to the first metal line and the second metal line which are the positive output and the sub output lines of the sense amplifier stage, respectively, From the positive output stage of the sense amplifier stage to the input terminal of the first latch is subjected to a lot of loading influence of the first metal line, and from the output terminal of the first latch to the PMOS transistor of the output driver provided to almost the loading of the first metal line The second latch means is provided so as not to be influenced, and the second latch means is provided from the output end of the second latch means so that the second metal line is hardly affected by the loading from the sub output end of the sense amplifier stage to the input end of the second latch means. Up to the NMOS transistor of the output driver is configured so that the second metal line is hardly affected by the loading of the second metal line. Shall be.
    Hereinafter, an embodiment of the present invention will be described in detail with reference to FIG. 2.
    The technical feature of the present invention is that the PMOS transistor whose driving ability is relatively lower than that of the NMOS transistor is prevented from being affected by the metal line loading, and the NMOS transistor is affected by the metal line loading, so that the driving of the PMOS transistor is performed. By driving the MOS transistors under better conditions, the pull-up stage of the output driver can be formed with a smaller MOS transistor.
    FIG. 2 is a schematic view showing an output stage structure according to an embodiment of the present invention. As shown in the drawing, in the present embodiment, the first metal line and the second metal, which are the positive and negative output lines of the sense amplifier stage 10, are illustrated in FIG. The first latch 20a and the second latch 20b are configured on the lines, respectively, so that the loading of each metal line is opposite to each other at the input and output of each latch.
    That is, the first latch 20a connected to the first metal line to which the positive output of the sense amplifier stage 10 is transmitted is connected from the positive output terminal (node A) of the sense amplifier stage 10 to the input terminal of the first latch 20a. The load of the first metal line is greatly affected, and from the output end of the first latch 20a to the PMOS transistor of the output driver, the first metal line is hardly affected by the loading of the first metal line.
    The second latch 20b connected to the second metal line to which the negative output of the sense amplifier stage 10 is transmitted is provided from the negative output terminal (node Ab) of the sense amplifier stage 10 to the input terminal of the second latch 20b. The second metal line is hardly affected by the loading of the second metal line, and from the output end of the second latch 20b to the enMOS transistor of the output driver, the second metal line is loaded.
    The operation of this embodiment having the configuration as described above will be described in detail.
    When the sense amplifier 10 reads 'High' data, its positive output node A is 'High' and its sub-output node Ab is 'Low'. At this time, the data of the node A reaches the first latch 20a which is delayed by the loading effect of the first metal line, and the node Ab reaches the second latch 20b with almost no effect.
    Subsequently, the data stored in the first latch 20a and the second latch 20b are transferred to the output driver 30 by a clock signal in the next cycle. The pull-up MOS transistor of the output driver 30 is transferred to the output driver 30. The data of the driving first latch 20a is transferred without the first metal line loading, and the data of the second latch 20b driving the pull-down NMOS transistor of the output driver 30 affects the loading of the second metal line. Received by them.
    Therefore, PMO transistors whose driving ability is relatively lower than NMOS transistors are driven by receiving data that is not influenced by the metal line, and thus, the PMO transistors are in a better condition than the NMOS transistors that receive data affected by metal line loading. As a result, it is not necessary to use a large PMOS transistor used in a general structure.
    If the sense amplifier reads 'low' data, this is the opposite of the above process, which can also reduce the size of the PMOS transistor.
    As described above, the present invention utilizes the difference in driving capability between the pull-up PMOS transistor and the pull-down NMOS transistor constituting the output driver, and the metal line loading from the sense amplifier stage to the output driver. By optimizing the size, that is, the size of the PMOS transistor, there is an effect of increasing the integration of synchronous memory devices employing the 2.5VI / O interface to cope with bit-wide.
    权利要求:
    Claims (1)
    [1" claim-type="Currently amended] The first latch means and the second latch means are respectively connected to the first metal line and the second metal line, which are the positive output and the negative output lines of the sense amplifier stage,
    The first latch means may be affected by the loading of the first metal line from the positive output end of the sense amplifier stage to the input end of the first latch, and the PMOS transistor of the output driver provided from the output end of the first latch. 1 Configure the connection so that it is hardly affected by the loading of the metalline.
    The second latch means is hardly influenced by the loading of the second metal line from the sub output end of the sense amplifier stage to the input end of the second latch means, and the enMOS transistor of the output driver provided from the output end of the second latch means. The synchronous memory device of claim 2, wherein the connection is configured such that the second metal line is hardly affected by the loading of the second metal line.
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    同族专利:
    公开号 | 公开日
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1996-12-24|Application filed by 김영환, 현대전자산업 주식회사
    1996-12-24|Priority to KR1019960071425A
    1998-09-25|Publication of KR19980052437A
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019960071425A|KR19980052437A|1996-12-24|1996-12-24|Synchronous memory device for size optimization of output drivers|
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